/*
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 * 
 * @Author: ipk518 121206530@qq.com
 * @Date: 2025-02-06 14:54:35
 * @LastEditors: ipk518 121206530@qq.com
 * @LastEditTime: 2025-02-11 16:57:40
 * @FilePath: /axilite_qspi/driver/xspi_sinit.c
 * @Description: 
 * ************佛祖保佑************
 * Copyright (c) 2025 by etws@quyujiang, All Rights Reserved. 
 */

/******************************************************************************
* Copyright (C) 2005 - 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

/*****************************************************************************/
/**
*
* @file xspi_sinit.c
* @addtogroup spi_v4_8
* @{
*
* The implementation of the XSpi component's static initialization
* functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who  Date     Changes
* ----- ---- -------- -----------------------------------------------
* 1.01a jvb  10/13/05 First release
* 1.11a wgr  03/22/07 Converted to new coding style.
*
* </pre>
*
******************************************************************************/

/***************************** Include Files *********************************/

#include "xspi.h"

#include "xstatus.h"
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <signal.h>
#include <fcntl.h>
#include <ctype.h>
#include <termios.h>
#include <sys/types.h>
#include <sys/mman.h>

#define XPAR_XSPI_NUM_INSTANCES	1

/* Canonical definitions for peripheral AXI_QUAD_SPI_0 */
#define XPAR_SPI_0_DEVICE_ID 0U
#define XPAR_SPI_0_BASEADDR 0x50000
#define XPAR_SPI_0_HIGHADDR 0x5FFFFU
#define XPAR_SPI_0_FIFO_EXIST 1U
#define XPAR_SPI_0_FIFO_DEPTH 16U
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0U
#define XPAR_SPI_0_NUM_SS_BITS 1U
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8U
#define XPAR_SPI_0_SPI_MODE 2U
#define XPAR_SPI_0_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_SPI_0_AXI4_BASEADDR 0U
#define XPAR_SPI_0_AXI4_HIGHADDR 0U
#define XPAR_SPI_0_XIP_MODE 0U
#define XPAR_SPI_0_USE_STARTUP 1U



/* Canonical definitions for peripheral AXI_QUAD_SPI_0 */

/*
* The configuration table for devices
*/

XSpi_Config XSpi_ConfigTable[] =
{
	{
		-1,
		XPAR_SPI_0_DEVICE_ID,
		XPAR_SPI_0_BASEADDR,
		NULL,
		XPAR_SPI_0_FIFO_EXIST,
		XPAR_SPI_0_SPI_SLAVE_ONLY,
		XPAR_SPI_0_NUM_SS_BITS,
		XPAR_SPI_0_NUM_TRANSFER_BITS,
		XPAR_SPI_0_SPI_MODE,
		XPAR_SPI_0_TYPE_OF_AXI4_INTERFACE,
		XPAR_SPI_0_AXI4_BASEADDR,
		XPAR_SPI_0_XIP_MODE,
		XPAR_SPI_0_USE_STARTUP,
		XPAR_SPI_0_FIFO_DEPTH
	}
};


#define FATAL do { fprintf(stderr, "Error at line %d, file %s (%d) [%s]\n", \
  __LINE__, __FILE__, errno, strerror(errno)); exit(1); } while(0)
 
#define MAP_SIZE sysconf(_SC_PAGESIZE)
#define MAP_MASK (MAP_SIZE - 1)

XSpi_Config *XSpi_LookupConfig(u16 DeviceId)
{
	XSpi_Config *CfgPtr = NULL;
	u32 Index;

	for (Index = 0; Index < XPAR_XSPI_NUM_INSTANCES; Index++) {
		if (XSpi_ConfigTable[Index].DeviceId == DeviceId) {
			CfgPtr = &XSpi_ConfigTable[Index];
			break;
		}
	}

	return CfgPtr;
}


int XSpi_Initialize(XSpi *InstancePtr, u16 DeviceId)
{
	XSpi_Config *ConfigPtr;	/* Pointer to Configuration ROM data */

	Xil_AssertNonvoid(InstancePtr != NULL);

	/*
	 * Lookup the device configuration in the temporary CROM table. Use this
	 * configuration info down below when initializing this component.
	 */
	ConfigPtr = XSpi_LookupConfig(DeviceId);
	if (ConfigPtr == NULL) {
		return XST_DEVICE_NOT_FOUND;
	}

	if((ConfigPtr->fd = open("/dev/xdma0_user", O_RDWR | O_SYNC)) == -1) FATAL;
    printf("/dev/xdma0_user opened.\n"); 
    fflush(stdout);
	
	/* Map one page */
    ConfigPtr->Map = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, ConfigPtr->fd, ConfigPtr->BaseAddress & ~MAP_MASK);
    if(ConfigPtr->Map == (void *) -1) FATAL;
    printf("Src address %p ,Memory mapped at address %p.\n", ConfigPtr->BaseAddress,ConfigPtr->Map); 
    fflush(stdout);
	
	ConfigPtr->BaseAddress = (UINTPTR)ConfigPtr->Map;

	return XSpi_CfgInitialize(InstancePtr, ConfigPtr,
				  ConfigPtr->BaseAddress);

}

